Praktikum Hardware/Software-Codesign

The HW/SW-Codesign Lab uses the reconfigurable processor flow from the company Tensilica to demonstrate the potential of HW/SW Codesign. The Tensilica Instruction Extension (TIE) is a description language that allows to modify the standard RISC/VLIW pipelines of the different baseline processors.

Out of the TIE description a modified compiler, assembler, linker, debugger and a cycle accurate processor simulator are generated. Thereby architecture modifications and their impact to the software can be analyzed with short turn-around times and manageable complexity. An energy and area estimator can be used to infer some estimates on the hardware complexity of the modified architecture without the need for setting up a complete RTL synthesis flow.