TU Dresden | Sommersemester 2021 Embedded Hardware System Design

Embedded Hardware System Design

Nowadays, the means of computation in datacenters are no longer homogeneous. Traditionally, only the General Purpose Processors were used to process the data. The current datacenters are moving towards heterogeneous computation where other components are integrated alongside GPPs. They are either GPGPUs (General Purpose Graphic Processing Units), dedicated hardware accelerators (like Google TPU, Tensor-Processing Unit) or a more generic reconfigurable platform for accelerators, FPGA (Field Programmable Gate Array). GPGPU proves to be very efficient in parallel processing in the big-data era with tremendous data bandwidth and processing power. However, they require hundreds of watts of power (each) to operate which significantly contribute to the plethora of problems in cooling and power management in datacenters. On the other end of the spectrum, dedicated hardware accelerators are extremely fast and power efficient for its very desired functionality. FPGAs sit in the middle of the spectrum to offer the best of both worlds: fast computation with inherently infinite parallelism, generic enough for (almost) any accelerator on the same platform with reconfigurability, and finally, energy-efficient with reasonable power consumption (40W on Microsoft datacenters). As a result, many companies have been investing in FPGA in their datacenter solutions such as Microsoft, Amazon, Baidu, Huawei, Ericsson, etc.


The aim of this module is to equip the students with the knowledge of hardware systems design. It starts with different ideas, flows, and steps involved in moving from a high-level system architecture specification models to a fully functional, optimized system on the FPGA. In order to fulfill this goal, the students need to have a different mindset in working with hardware. It’s no longer sequential, everything is parallelized. The insights into different algorithms and techniques in every step of building the hardware (turning hardware description language model to logic elements, mapping and placing them to FPGA resources, connecting those resources to realize a working system) are discussed. These are the foundations for the students to critically analyze and successfully design a hardware system on the FPGA. 

Nowadays, the means of computation in datacenters are no longer homogeneous. Traditionally, only the General Purpose Processors were used to process the data. The current datacenters are moving towards heterogeneous computation where other components are integrated alongside GPPs. They are either GPGPUs (General Purpose Graphic Processing Units), dedicated hardware accelerators (like Google TPU, Tensor-Processing Unit) or a more generic reconfigurable platform for accelerators, FPGA (Field Programmable Gate Array). GPGPU proves to be very efficient in parallel processing in the big-data era with tremendous data bandwidth and processing power. However, they require hundreds of watts of power (each) to operate which significantly contribute to the plethora of problems in cooling and power management in datacenters. On the other end of the spectrum, dedicated hardware accelerators are extremely fast and power efficient for its very desired functionality. FPGAs sit in the middle of the spectrum to offer the best of both worlds: fast computation with inherently infinite parallelism, generic enough for (almost) any accelerator on the same platform with reconfigurability, and finally, energy-efficient with reasonable power consumption (40W on Microsoft datacenters). As a result, many companies have been investing in FPGA in their datacenter solutions such as Microsoft, Amazon, Baidu, Huawei, Ericsson, etc.
The aim of this module is to equip the students with the knowledge of hardware systems design. It starts with different ideas, flows, and steps involved in moving from a high-level system architecture specification models to a fully functional, optimized system on the FPGA. In order to fulfill this goal, the students need to have a different mindset in working with hardware. It’s no longer sequential, everything is parallelized. The insights into different algorithms and techniques in every step of building the hardware (turning hardware description language model to logic elements, mapping and placing them to FPGA resources, connecting those resources to realize a working system) are discussed. These are the foundations for the students to critically analyze and successfully design a hardware system on the FPGA. 

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  • This content will be available from 31/03/2021 10:23 AM until 30/10/2021 10:23 AM.

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