Embedded Hardware Systems Design Practical 2022/23

Welcome (Winter 2023-24)

Welcome to the Praktikum Embedded Hardware System Design course for Winter 2023-24. This module is designed as a follow-up to the Embedded Hardware System Design (lecture and seminar) offered in the summer semester. However, it is also suitable for other participants who did not attend the lecture and seminar courses. Previously, the participants learned about the knowledge of hardware systems design. It started with different ideas, flows, and steps in moving from a high-level system architecture specification model to a fully functional, optimized system on the FPGA. The insights into different algorithms and techniques in every step of building the hardware (turning behavioral models to logic elements, mapping and placing them to FPGA resources, connecting those resources to realize a working system) were discussed.

In this module, the participants will be exposed to practical challenges involved in the various aspects of designing hardware for embedded systems. The goal of this module is to have hands-on practice in implementing various stages of embedded hardware design. The current course will follow a project-based approach, where the participants will be evaluated on their implementation of two projects. The first project will be related to HDL- and HLS-based embedded system designing using Vivado, and the second project will focus on logic synthesis and technology mapping using ABC. For this purpose, the course will be divided into two 7-weeks parts each. In each part, we will initially have three-week tutorials to discuss the relevant tools and skills, followed by four-week time to complete the projects. The project list is given below:

HDL- and HLS-based System Design (Part 1)

1. Conv2D filter for Convolutional layer and accuracy-performance trade-off using precision scaling: This project focuses on initially implementing a Conv2D operator and then utilizing it to implement a Convolutional layer. The implementation should be tested on an Ultra96 board using a test dataset. Furthermore, precision scaling would be considered to explore accuracy-performance trade-offs. Students can consider both HDL and HLS for the implementation.

Systolic Array Accelerator for Matrix Multiplication (Part 1)

The accelerator can be designed with an HDL- or HLS-based approach. In the case of an HLS-based approach, it would be nice if you could also explore the impact of some of the HLS pragmas. Keep the dimensions of the systolic array as design time parameters. Keep the granularity of the systolic array on a PE level. This means there should be distinct instances of PEs in the generated RTL according to the total number of PEs described by the design-time dimensions. Test the implemented systolic array by providing different sizes of matrices.

Logic Synthesis-based project (Part 2)

1. A canonical form is a compact representation of a boolean expression. For example, a sum-of-product (SOP) form of (a*!b)+(!a*b)+(a*b)) can be reduced to (a+b). Methods for finding canonical form includes using karnaugh maps, reduced-order binary decision trees, quine mccluskey approach. Given a sum-of-products form of a boolean expresion, you have to find its canonical form. Write a C/C++ or python program to implement Quine-Mccluskey Approach to find the canonical form of a given SOP form. I would expect your code to work for more than 6 variables expression. You can find a lot of material on Quine-Mccluskey approach.