Deep Neural Network Hardware

This course focuses on the design of hardware accelerators for deep neural networks (DNN), ranging from architectures to arithmetic building blocks. Aspects of hardware/software codesign are covered, as well as DNN deployment on hardware accelerators. Selected optimization techniques for DNN accelerators and upcoming accelerator approaches are introduced.

The course consists of a weekly lecture (2026: Monday, 13:00-14:30 in room BAR/106) and an accompanying exercise (2026: three exercise groups on Thursday: 9:20-10:50 in room APB/E008/U, 13:00-14:30 in room BAR/I86C and 14:50-16:20 again in room BAR/I86C). It is completed by a written examination.

Materials for the course are published here on OPAL during the semester.