Deep Neural Network Hardware

TU Dresden, Chair for Highly-Parallel VLSI Systems and Neuromicroelectronics | Sommersemester Deep Neural Network Hardware

This course focuses on the design of hardware accelerators for deep neural networks (DNN), ranging from architectures to arithmetic building blocks. Aspects of hardware/ software codesign are covered, as well as DNN deployment on hardware accelerators. Selected optimization techniques for DNN accelerators and upcoming accelerator approaches are introduced.


The course consists of a weekly lecture (2024: Monday, 13:00-14:30 in room ZEU/0118/H) and an accompanying exercise (2024: two exercise groups on Thursday, 13:00-14:30 in room SCH/A285/U and on Thursday, 14:50-16:20 in room SCH/A214/U). It is completed by a written examination.


Materials for this course are published here.

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