Hardware Software Co-design Advanced

This course introduces modern parallel DSP architectures and algorithms with a strong focus on how implementation platforms shape algorithm design and performance. Students will learn how to parallelize both recursive and non‑recursive DSP algorithms, such as FIR and IIR filters, and apply a range of acceleration strategies tailored to the underlying processor architecture. The course covers SIMD, VLIW, and vector processor architectures in depth, including their instruction models and execution paradigms, and discusses both static and dynamic instruction scheduling techniques.

A central theme is understanding how architectural features influence throughput and efficiency. To this end, the course compares SIMD‑VLIW processors with multi‑lane and SIMD functional‑unit-based vector processors, highlighting differences in pipeline flow, instruction issue, and control overhead. Particular emphasis is placed on data movement: students will analyze and compare memory hierarchies, data access patterns, and data transfer mechanisms, and examine how memory and compute bandwidth jointly constrain parallel implementations of different DSP kernels. The roofline performance model is introduced as a unifying framework to relate achievable performance to arithmetic intensity, enabling students to identify whether a given implementation is memory‑bound or compute‑bound and to reason systematically about optimization opportunities.