Praktikum Hardware/Software-Codesign
Summer Semester 2026
IMPORTANT NOTICE: NES students, please register for the lab course using the link below.
The HW/SW Codesign Lab employs Tensilica’s reconfigurable processor flow to illustrate the potential of hardware/software co-design. The Tensilica Instruction Extension (TIE) serves as a description language that enables systematic modification of the standard RISC/VLIW pipelines of various baseline processors.
From the TIE description, a modified compiler, assembler, linker, debugger, and a cycle-accurate processor simulator are generated. In this way, architecture modifications and their impact on the software can be analyzed with short turnaround times and manageable complexity. An energy and area estimator can also be used to infer estimates of the hardware complexity of the modified architecture without the need to set up a complete RTL synthesis flow.
First Lab Session on 24th of April
First Lab Session:
Date: 24.04.2026
Time: 7.30-9:00 (1.DS)
Location: POT/0106/U
Second Lab Session:
Date: 08.05.2026
Time: 7.30-9:00 (1.DS)
Location: POT/0106/U